9618Paper 1 · Theory Fundamentals§4.1, §4.2, §4.3

4. Processor Fundamentals

Von Neumann CPU, registers, buses, the FDE cycle with register transfer notation, interrupts, assembly language, addressing modes and bit manipulation.

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Statometer76BankerNext Paper 189%

Marks a paper13.1 · 18%Rank#6 of 12 · #4 on P1Trend · last 12↘Full stats

Everything for this topic — study hub

AS Level · 9618 · Paper 1

Statometer — what 33 real papers say about this topic and each of its 4 syllabus bullets

Banker · #6 of 12 in AS Level · recomputed with every new session

Banker#6 of 12 in AS Level#4 on Paper 1↘ Easing

Set in nearly every paper and worth a big slice of it — revise first, expect it.

Next Paper 1: 89%; 9 in 10 chance it is set
Marks a paper: 13.1 / 75; 18% of Paper 1 · fair share 13%
Appeared in: 32 / 33; Paper 1 sittings 2021–2026
Last set: May/Jun 2026; 9618/13 · Q7 · 9 marks · 11-series streak

Marks in each of the last 12 Paper 1 sittingsOct/Nov 24 → May/Jun 26

What the papers say

Set in 32 of 33 Paper 1 sittings on the current syllabus — treat it as certain.
Worth about 13.1 marks a paper (18% of Paper 1, 1.4× its fair share).
Last set May/Jun 2026 · 9618/13 · Q7 for 9 marks — in the most recent series.
Set in each of the last 11 series without a miss.
Easing off: about 16.3 marks a paper earlier, 10.8 in the latest years — still examined, just smaller.
Lives on “Complete” and “Identify” — 79% of its questions: you must produce something — code, a diagram, a table — practise doing it, not reading it.
65% of its questions involve a diagram, table or figure — practise with pen and paper.
67% of its questions are set out as code, pseudocode or a table to complete.
Its biggest question so far: 17 marks (May/Jun 2021 · 9618/12 · Q5).
Inside the topic, §4.1 CPU architecture carries the most marks (50%) and §4.3 Bit manipulation the least (3%).
It is examined mostly as AO1 (Knowledge & understanding, 57%), the rest AO2 (43%) — definitions and descriptions in syllabus words score.
The examiner has commented on 31 of its questions — read “What the examiner said” before you practise.

Command words

Share of questions using the word (a question can use several). What each wants →

Question shapes

≤ 6 mk5
7–9 mk19
10–12 mk15
13–15 mk7
16+ mk2

Average 9.8 marks a question · 65% with a figure or table · 67% with code · biggest 17 marks

Assessment objectives — how it is examined

Every part of every current-syllabus question filed under Cambridge's AO1 / AO2 / AO3 (from its command word and what it asks you to do), so you know whether this topic pays for definitions, for applying, or for judging and building.

AO1 57%

AO2 43%

AO1 Knowledge & understanding
AO2 Apply & analyse
AO3 Design, program & evaluate

Paper 1 as a whole

Paper 1	Syllabus	Measured
AO1 Knowledge & understanding	60%	68%
AO2 Apply & analyse	40%	32%
AO3 Design, program & evaluate	0%	0%

Syllabus = Cambridge's grid; measured = the bank's current-syllabus papers.

Inside the topic — every syllabus bullet, measured

Each part of each question is filed under the bullet it examines; the numbers are per Paper 1 sitting, exactly like the topic's. Open a bullet for its own Statometer.

4.1CPU architecture#4 of 25 on Paper 1Banker · 8580% next paper5.7 marks29/33 sittings↘ May/Jun 2026Banker · 8580%
5.7 · 50% of topic29/33May/Jun 2026latest series · ↘
Asked in nearly every paper — the bullet to know cold.Syllabus: Von Neumann and the stored program concept; registers (PC, MDR, MAR, ACC, IX, CIR, status); ALU, CU, clock, IAS; the three buses; performance factors; USB, HDMI and VGA ports
Next Paper 1
80%
8 in 10
Marks a paper
5.7
8% of the paper · 50% of the topic
Asked in
29 / 33
Paper 1 sittings · 42 questions
Last asked
May/Jun 2026
9618/11 · Q3 · 2 marks · 11-series streak
Asked in 29 of 33 Paper 1 sittings — nearly every paper.
About 5.7 marks a paper (8% of Paper 1; 50% of the topic's marks across its 4 bullets).
Last asked May/Jun 2026 · 9618/11 · Q3 (2 marks) — in the most recent series.
Asked in each of the last 11 series.
Easing: 7.5 → 4.3 marks a paper.
Usually “Complete” or “Describe”: you must produce something — code, a diagram, a table — practise doing it, not reading it.
Biggest chunk of marks so far: 12 in Oct/Nov 2023 · 9618/11 · Q5.
It is examined mostly as AO1 (Knowledge & understanding, 66%), the rest AO2 (34%) — definitions and descriptions in syllabus words score.
Last 12 sittings↘ Easing
Assessment objectives
AO1 66%
AO2 34%
AO1 Knowledge & understanding
AO2 Apply & analyse
AO3 Design, program & evaluate
Complete52%
Describe48%
Identify45%
Explain36%
Practise its 42 questions Biggest: 12 marks · Oct/Nov 2023
4.1The fetch–execute cycle in register transfer notation; interrupts#23 of 25 on Paper 1Occasional · 2735% next paper1.3 marks14/33 sittings↘ May/Jun 2025Occasional · 2735%
1.3 · 13% of topic14/33May/Jun 20252 series ago · ↘
Rotated in occasionally — the bullet students skip and then meet.Syllabus: causes, applications, the ISR, and when and how interrupts are detected and handled
Next Paper 1
35%
1 in 4
Marks a paper
1.3
2% of the paper · 13% of the topic
Asked in
14 / 33
Paper 1 sittings · 15 questions
Last asked
May/Jun 2025
9618/13 · Q2 · 2 marks · 2 series ago
Asked in 14 of 33 Paper 1 sittings — roughly one paper in 2.
About 1.3 marks a paper (2% of Paper 1; 13% of the topic's marks across its 4 bullets).
Last asked May/Jun 2025 · 9618/13 · Q2 (2 marks), 2 seriess ago.
Easing: 2.4 → 0.6 marks a paper.
Usually “Describe” or “Identify”: full sentences with a reason, not one-word answers.
Biggest chunk of marks so far: 6.5 in May/Jun 2022 · 9618/13 · Q2.
It is examined almost entirely as AO1 (Knowledge & understanding, 81%) — definitions and descriptions in syllabus words score.
Last 12 sittings↘ Easing
Assessment objectives
AO1 81%
AO2 19%
AO1 Knowledge & understanding
AO2 Apply & analyse
AO3 Design, program & evaluate
Describe60%
Identify53%
Explain47%
Complete47%
Practise its 15 questions Biggest: 6.5 marks · May/Jun 2022
4.2Assembly language#7 of 25 on Paper 1Banker · 7680% next paper4.2 marks28/33 sittings→ May/Jun 2026Banker · 7680%
4.2 · 34% of topic28/33May/Jun 2026latest series · →
Asked in nearly every paper — the bullet to know cold.Syllabus: machine code; the two-pass assembler; tracing programs; instruction groups (data movement, I/O, arithmetic, jumps, compare); the five addressing modes
Next Paper 1
80%
8 in 10
Marks a paper
4.2
6% of the paper · 34% of the topic
Asked in
28 / 33
Paper 1 sittings · 28 questions
Last asked
May/Jun 2026
9618/13 · Q7 · 4 marks · 11-series streak
Asked in 28 of 33 Paper 1 sittings — about 8 papers in 10.
About 4.2 marks a paper (6% of Paper 1; 34% of the topic's marks across its 4 bullets).
Last asked May/Jun 2026 · 9618/13 · Q7 (4 marks) — in the most recent series.
Asked in each of the last 11 series.
Usually “Complete” or “Write”: you must produce something — code, a diagram, a table — practise doing it, not reading it.
Biggest chunk of marks so far: 8 in May/Jun 2025 · 9618/13 · Q5.
It is examined mostly as AO2 (Apply & analyse, 73%), the rest AO1 (27%) — you must apply it to the given data or scenario — work it out, trace it, explain it in context.
Last 12 sittings→ Steady
Assessment objectives
AO1 27%
AO2 73%
AO1 Knowledge & understanding
AO2 Apply & analyse
AO3 Design, program & evaluate
Complete64%
Write50%
Identify36%
Trace25%
Practise its 28 questions Biggest: 8 marks · May/Jun 2025
4.3Bit manipulation#25 of 25 on Paper 1Occasional · 2036% next paper0.6 marks9/33 sittings→ May/Jun 2026Occasional · 2036%
0.6 · 3% of topic9/33May/Jun 2026latest series · →
Rotated in occasionally — the bullet students skip and then meet.Syllabus: logical, arithmetic and cyclic shifts; AND, OR and XOR masks to test and set bits; monitoring and controlling devices with bit patterns
Next Paper 1
36%
1 in 4
Marks a paper
0.6
1% of the paper · 3% of the topic
Asked in
9 / 33
Paper 1 sittings · 9 questions
Last asked
May/Jun 2026
9618/13 · Q7 · 5 marks · 4-series streak
Asked in 9 of 33 Paper 1 sittings — roughly one paper in 4.
About 0.6 marks a paper (1% of Paper 1; 3% of the topic's marks across its 4 bullets).
Last asked May/Jun 2026 · 9618/13 · Q7 (5 marks) — in the most recent series.
Asked in each of the last 4 series.
Usually “Write” or “Complete”: you must produce something — code, a diagram, a table — practise doing it, not reading it.
Biggest chunk of marks so far: 5 in May/Jun 2026 · 9618/13 · Q7.
It is examined mostly as AO2 (Apply & analyse, 66%), the rest AO1 (35%) — you must apply it to the given data or scenario — work it out, trace it, explain it in context.
Last 12 sittings→ Steady
Assessment objectives
AO1 35%
AO2 66%
AO1 Knowledge & understanding
AO2 Apply & analyse
AO3 Design, program & evaluate
Write67%
Complete44%
Identify44%
Trace33%
Practise its 9 questions Biggest: 5 marks · May/Jun 2026

11% of the topic's marks sit in question parts that belong to another topic (scenario questions cross sections) or that no bullet claims; they count for the topic, not for a bullet.

Marks a paper, year by year

212223242526

By exam series

May/Jun17/18 · 12.4 mk
Oct/Nov15/15 · 16.5 mk

Practise 48 real questions Smart Notes Quiz Flashcards Every topic on the Statometer

What you need to know4syllabus §4.1, §4.2, §4.3

4.1CPU architecture — Von Neumann and the stored program concept; registers (PC, MDR, MAR, ACC, IX, CIR, status); ALU, CU, clock, IAS; the three buses; performance factors; USB, HDMI and VGA ports
4.1The fetch–execute cycle in register transfer notation; interrupts — causes, applications, the ISR, and when and how interrupts are detected and handled
4.2Assembly language — machine code; the two-pass assembler; tracing programs; instruction groups (data movement, I/O, arithmetic, jumps, compare); the five addressing modes
4.3Bit manipulation — logical, arithmetic and cyclic shifts; AND, OR and XOR masks to test and set bits; monitoring and controlling devices with bit patterns

Video lectures49ZAK's YouTube channel · play here

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Infographics5draw these the way the examiner expects · download as PNG

Two's complement, overflow & shifts

O LevelAS

Von Neumann architecture

O LevelAS

Fetch–Decode–Execute cycle

O LevelAS

How an interrupt is handled

O LevelAS

Assembly language & addressing modes

Browse all infographics →

Key terms15use these exact words in the exam

registerMARMDRCIRPCACCRTNinterruptassemblyopcodeoperandaddressing modelogical shiftarithmetic shiftmask

Dotted terms are defined in the glossary.

Code help4referenced to the Cambridge pseudocode guide

Assembly: add two numbers and store

assembly Run in Assembler

LDD 200    ; load contents of address 200 into ACC (direct)
ADD 201    ; add contents of address 201
STO 202    ; store ACC at address 202
END

💡 Direct addressing: the operand is an address. LDM #5 would load the number 5 itself (immediate).

Assembly: loop with a counter and conditional jump

assembly Run in Assembler

      LDM #0     ; ACC ← 0 (total)
      STO 300
      LDM #5     ; counter
      STO 301
LOOP: LDD 300
      ADD 301    ; total ← total + counter
      STO 300
      LDD 301
      DEC ACC    ; counter ← counter − 1
      STO 301
      CMP #0
      JPN LOOP   ; jump if not equal to 0
      LDD 300
      OUT
      END

Bit masking to test a flag

assembly Run in Assembler

LDD 400        ; status byte
AND #B00000100 ; keep only bit 2
CMP #0
JPE OFF        ; bit 2 was 0
; ... bit 2 set
OFF: END

Simulate shifts and masks in pseudocode

pseudocode Run in Playground

DECLARE ACC : INTEGER
ACC ← 45          // 0010 1101
OUTPUT ACC * 2    // LSL #1 → 90
OUTPUT ACC DIV 4  // LSR #2 → 11
OUTPUT ACC MOD 16 // AND #B00001111 → 13 (low nibble)

Playground examples2runnable programs for this topic

Bit manipulation — test, set and clear a bit
DIV and MOD by powers of 2 do the job of shifts and masks (AND/OR/XOR) from the 9618 instruction set.
ASPseudocodeTheory in code 9618 §4.4
Run
Fetch–decode–execute simulator
A tiny CPU: PC and ACC registers, instructions in memory, one loop that fetches, decodes with CASE and executes.
ASPseudocodeTheory in code 9618 §4.1, §4.3
Run

Assembler34programs to step through the CPU simulator

Add two numbers in memory
The classic first program: load, add, store. Watch ACC change and address 202 get written.
ASLoading & storing 9618 §4.2
Run
LDM #n vs LDD n — number or address?
The most-tested distinction: LDM #200 loads the number 200, LDD 200 loads the CONTENTS of address 200.
ASLoading & storing 9618 §4.2
Run
Symbolic addresses (labels) instead of numbers
Label your data and jump targets — the assembler turns each label into an address. Check the memory panel to see where NUM1 landed.
ASLoading & storing 9618 §4.2, §5.2 assembler
Run
LDR #n and MOV IX — filling the index register
Two ways to set IX: load a number straight into it (LDR) or copy ACC across (MOV).
ASLoading & storing 9618 §4.2
Run
Swap two memory locations
No swap instruction exists — do it through ACC with a temporary location, like Temp ← X in pseudocode.
ASLoading & storing 9618 §4.2
Run
ADD and SUB with immediate values
ADD #n adds the number n; ADD n adds the contents of address n. Both forms are in the syllabus.
ASArithmetic 9618 §4.2
Run
INC and DEC on ACC and IX
Both registers can be incremented and decremented directly — the usual way to move a counter or an index.
ASArithmetic 9618 §4.2
Run
Multiply by repeated addition
There is no MUL — 6 × 4 is 4 added six times, counted down with DEC and CMP/JPN.
ASA2Arithmetic 9618 §4.2
Run
Negative results and two's complement
5 − 12 = −7. Look at the binary view of ACC: 11111001 is −7 in 8-bit two's complement.
ASArithmetic 9618 §1.1, §4.2
Run
Overflow — when the result no longer fits
In an 8-bit accumulator 200 + 100 = 300 cannot be represented. The simulator keeps the value but raises the overflow flag, exactly what the exam wants you to explain.
ASArithmetic 9618 §1.1 overflow
Run
Immediate addressing
The operand IS the value. LDM #25 puts 25 in ACC — no memory read happens in the execute stage.
ASA2Addressing modes 9618 §4.2, §20.1
Run
Direct addressing
The operand is the address of the value. LDD 200 reads memory location 200. Watch MAR/MDR in the execute stage.
ASA2Addressing modes 9618 §4.2, §20.1
Run
Indirect addressing (LDI)
The operand holds the address of the address. [200] = 300, so LDI 200 loads [300]. A pointer in assembly.
ASA2Addressing modes 9618 §4.2, §20.1
Run
Indexed addressing (LDX) — walking an array
Address = operand + IX. With IX = 0, 1, 2… LDX 300 visits 300, 301, 302 — how a loop reads an array.
ASA2Addressing modes 9618 §4.2, §20.1
Run
All five addressing modes in one program
Immediate, direct, indirect, indexed and relative, one after another — the summary table you should be able to reproduce in Paper 3.
A2Addressing modes 9618 §4.2, §20.1
Run
IF … THEN … ELSE with CMP and JPE
Compare sets a flag; JPE / JPN choose the path. This is how selection is built in a low-level language.
ASCompare & jump 9618 §4.2
Run
Counted loop: total 1 to 5
A FOR loop in assembly — counter in memory, CMP against the limit, JPN back to the top.
ASCompare & jump 9618 §4.2
Run
Sum an array — the working idiom
Keep the loop counter in memory alongside IX: the counter is compared, IX does the indexing. Ends when COUNT = 0.
ASA2Compare & jump 9618 §4.2
Run
Linear search through memory
Search for 30 in an array of 5 using LDX; output Y if found, N if not. Change TARGET to try both paths.
ASA2Compare & jump 9618 §4.2
Run
CMI — compare through a pointer
CMI 200 compares ACC with the value at the address stored in 200 — indirect addressing for a compare.
ASA2Compare & jump 9618 §4.2
Run
AND mask — test whether a bit is set
AND with B00000100 keeps only bit 2. If the result is 0 the bit was clear. Watch the binary working in the execute panel.
ASBit manipulation 9618 §4.3
Run
OR — set a bit without touching the others
OR with B00010000 forces bit 4 to 1 and leaves the rest alone.
ASBit manipulation 9618 §4.3
Run
XOR — toggle bits and clear ACC
XOR flips every bit where the mask has a 1; XOR-ing a value with itself gives 0 (a classic trick).
ASBit manipulation 9618 §4.3
Run
LSL / LSR — multiply and divide by powers of 2
Shifting left 1 doubles, right 1 halves (integer). 6 ≪ 2 = 24, 24 ≫ 3 = 3.
ASBit manipulation 9618 §4.3
Run
Bits lost off the end of a logical shift
B11000011 shifted left 2 loses its two top 1s: the result is B00001100. Logical shifts never bring them back.
ASBit manipulation 9618 §4.3
Run
Clear one bit with AND and a mask
To clear bit 0 AND with B11111110 — every bit kept except the one under the 0.
ASBit manipulation 9618 §4.3
Run
IN and OUT — echo a character
IN reads one keyboard character into ACC as its ASCII code; OUT prints the character whose code is in ACC.
ASInput & output 9618 §4.2
Run
Lower-case to upper-case with SUB #32
ASCII 'a' is 97 and 'A' is 65 — the difference is 32, so subtract it (or AND with B11011111).
ASInput & output 9618 §4.2, §1.2 ASCII
Run
Print a string stored in memory
Characters live at consecutive addresses, ending with 0. LDX + INC IX walks them until the terminator.
ASA2Input & output 9618 §4.2
Run
Count how many characters were typed
Read characters until a full stop; count them and output the count as a digit (count + 48 = its ASCII).
ASA2Input & output 9618 §4.2
Run
Trace question: what is in 320 at the end?
Typical Paper 1 question. Trace ACC and the memory locations, then check against the simulator's trace table.
ASExam-style traces 9618 §4.2
Run
Trace question: loop with JPN
Complete the trace table for ACC and address 500 — how many times does the loop body run?
ASExam-style traces 9618 §4.2
Run
Trace question: masks and shifts
Paper 1 bit-manipulation trace: show ACC in binary after each instruction.
ASExam-style traces 9618 §4.3
Run
Trace question: indirect and indexed together (A2)
Paper 3 style: combine LDI, LDX and CMI and give the final contents of the registers.
A2Exam-style traces 9618 §20.1
Run

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Quiz: Processor Fundamentals (50)🃏 Flashcards: mix this topic (70)🧠 CPU architecture, registers & FDE with RTN (29)⚙️ Assembly language & addressing modes (26)🎚️ Bit manipulation — shifts & masks (15)Past-paper questions (48)🧠 Assembler & CPU simulator 🔁 Fetch–execute in RTN + interrupts 🎭 Bit masks & shifts

Everything for this topic — study hub

Statometer — what 33 real papers say about this topic and each of its 4 syllabus bullets

What you need to know4syllabus §4.1, §4.2, §4.3

Video lectures49ZAK's YouTube channel · play here

Addressing modes · Immediate, Direct, Indirect, and Indexed · AS/A Level

Assembly Instructions · Part 2 · Groups · AS/A Level

Assembly Instructions · Part 1 · Addressing Modes · AS/A Level

Chapter 4 Topical Past Papers 2 · Assembly Language · Instruction Set · OA Level

Two Pass Assembler · LDV/LOAD Relative Instruction · Symbol Table · A/AS Level

Processor Fundamentals · Part 9 · Topical PP - 1 · 4.1 & 4.3 · A Level

Infographics5draw these the way the examiner expects · download as PNG

Key terms15use these exact words in the exam

Code help4referenced to the Cambridge pseudocode guide

Playground examples2runnable programs for this topic

Assembler34programs to step through the CPU simulator

Ready to check you know it?