Skip to content
9618Paper 3 · Advanced Theory§15.1, §15.2

15. Hardware and Virtual Machines

RISC vs CISC, pipelining, parallel processing (SISD/SIMD/MISD/MIMD), massively parallel computers, virtual machines — plus Boolean algebra, De Morgan's laws, Karnaugh maps, adders and flip-flops.

Read the Smart Notes Watch lectures (20) Ask the corner
Statometer68CoreNext Paper 395%
Marks a paper12.3 · 16%Rank#5 of 8 · #3 on P3Trend · last 12↘Oct/Nov 24 · 31: 14 · Oct/Nov 24 · 32: 13 · Oct/Nov 24 · 33: 14 · May/Jun 25 · 31: 8 · May/Jun 25 · 32: 8 · May/Jun 25 · 33: 8 · Oct/Nov 25 · 31: 9 · Oct/Nov 25 · 32: 9 · Oct/Nov 25 · 33: 8 · May/Jun 26 · 31: 13 · May/Jun 26 · 32: 12 · May/Jun 26 · 33: 13 marks9 in 10 chance in the next paper

Everything for this topic — study hub

A2 Level · 9618 · Paper 3

This topic is rows 6–7 of the study route.Open it on your study route

Statometer — what 32 real papers say about this topic and each of its 2 syllabus bullets

Core · #5 of 8 in A2 Level · recomputed with every new session

68CORE
Core#5 of 8 in A2 Level#3 on Paper 3↘ Easing

A regular, well-paid topic — you cannot afford a gap here.

Next Paper 3
95%
9 in 10 chance it is set
Marks a paper
12.3 / 75
16% of Paper 3 · fair share 17%
Appeared in
32 / 32
Paper 3 sittings 2021–2026
Last set
May/Jun 2026
9618/33 · Q6 · 8 marks · 11-series streak
Marks in each of the last 12 Paper 3 sittingsOct/Nov 24 → May/Jun 26
Oct/Nov 24 · 31: 14 marksOct/Nov 24 · 32: 13 marksOct/Nov 24 · 33: 14 marksMay/Jun 25 · 31: 8 marksMay/Jun 25 · 32: 8 marksMay/Jun 25 · 33: 8 marksOct/Nov 25 · 31: 9 marksOct/Nov 25 · 32: 9 marksOct/Nov 25 · 33: 8 marksMay/Jun 26 · 31: 13 marksMay/Jun 26 · 32: 12 marksMay/Jun 26 · 33: 13 marks

What the papers say

  • Set in 32 of 32 Paper 3 sittings on the current syllabus — treat it as certain.
  • Worth about 12.3 marks a paper (16% of Paper 3).
  • Last set May/Jun 2026 · 9618/33 · Q6 for 8 marks — in the most recent series.
  • Set in each of the last 11 series without a miss.
  • Easing off: about 14 marks a paper earlier, 12.2 in the latest years — still examined, just smaller.
  • Lives on “Complete” and “Write” — 71% of its questions: you must produce something — code, a diagram, a table — practise doing it, not reading it.
  • 73% of its questions involve a diagram, table or figure — practise with pen and paper.
  • 63% of its questions are set out as code, pseudocode or a table to complete.
  • Its biggest question so far: 10 marks (Oct/Nov 2024 · 9618/31 · Q7).
  • Inside the topic, §15.2 Boolean algebra and logic circuits carries the most marks (71%) and §15.1 Processors, parallel processing and virtual machines the least (29%).
  • It is examined mostly as AO2 (Apply & analyse, 54%), the rest AO1 (46%) — you must apply it to the given data or scenario — work it out, trace it, explain it in context.
  • The examiner has commented on 89 of its questions — read “What the examiner said” before you practise.

Command words

Share of questions using the word (a question can use several). What each wants →

Question shapes

  • ≤ 6 mk32
  • 7–9 mk30
  • 10–12 mk42
  • 13–15 mk11
  • 16+ mk5

Average 9 marks a question · 73% with a figure or table · 63% with code · biggest 10 marks

Assessment objectives — how it is examined

Every part of every current-syllabus question filed under Cambridge's AO1 / AO2 / AO3 (from its command word and what it asks you to do), so you know whether this topic pays for definitions, for applying, or for judging and building.

  • AO1 Knowledge & understanding
  • AO2 Apply & analyse
  • AO3 Design, program & evaluate

Paper 3 as a whole

Paper 3SyllabusMeasured
AO1 Knowledge & understanding60%54%
AO2 Apply & analyse40%46%
AO3 Design, program & evaluate0%0%

Syllabus = Cambridge's grid; measured = the bank's current-syllabus papers.

Inside the topic — every syllabus bullet, measured

Each part of each question is filed under the bullet it examines; the numbers are per Paper 3 sitting, exactly like the topic's. Open a bullet for its own Statometer.

  • 15.1Processors, parallel processing and virtual machines#6 of 14 on Paper 3Regular · 5265% next paper3.5 marks22/32 sittings→ May/Jun 2026

    Set most sessions for a few marks; know the definition and one example.Syllabus: RISC vs CISC and interrupt handling; pipelining; SISD, SIMD, MISD, MIMD; massively parallel computers; virtual machines and their limits

    Next Paper 3
    65%
    6 in 10
    Marks a paper
    3.5
    5% of the paper · 29% of the topic
    Asked in
    22 / 32
    Paper 3 sittings · 48 questions
    Last asked
    May/Jun 2026
    9618/33 · Q4 · 5 marks
    • Asked in 22 of 32 Paper 3 sittings — about 7 papers in 10.
    • About 3.5 marks a paper (5% of Paper 3; 29% of the topic's marks across its 2 bullets).
    • Last asked May/Jun 2026 · 9618/33 · Q4 (5 marks) — in the most recent series.
    • Usually “Describe” or “Explain”: full sentences with a reason, not one-word answers.
    • Biggest chunk of marks so far: 8 in May/Jun 2024 · 9618/31 · Q11.
    • It is examined almost entirely as AO1 (Knowledge & understanding, 97%) — definitions and descriptions in syllabus words score.
    Last 12 sittings→ Steady
    Oct/Nov 24 · 31: 4 marksOct/Nov 24 · 32: 4 marksOct/Nov 24 · 33: 4 marksMay/Jun 25 · 31: 0 marksMay/Jun 25 · 32: 0 marksMay/Jun 25 · 33: 0 marksOct/Nov 25 · 31: 0 marksOct/Nov 25 · 32: 0 marksOct/Nov 25 · 33: 0 marksMay/Jun 26 · 31: 4 marksMay/Jun 26 · 32: 4 marksMay/Jun 26 · 33: 5 marks

    Assessment objectives

    • AO1 Knowledge & understanding
    • AO2 Apply & analyse
    • AO3 Design, program & evaluate
    • Describe44%
    • Explain33%
    • State27%
    • Complete25%
    Practise its 48 questionsBiggest: 8 marks · May/Jun 2024
  • 15.2Boolean algebra and logic circuits#2 of 14 on Paper 3Banker · 9791% next paper8.8 marks30/32 sittings↘ May/Jun 2026

    Asked in nearly every paper — the bullet to know cold.Syllabus: truth tables for circuits including half and full adders; SR and JK flip-flops as storage elements; Boolean algebra and De Morgan's laws; Karnaugh maps

    Next Paper 3
    91%
    9 in 10
    Marks a paper
    8.8
    12% of the paper · 71% of the topic
    Asked in
    30 / 32
    Paper 3 sittings · 72 questions
    Last asked
    May/Jun 2026
    9618/33 · Q6 · 8 marks · 11-series streak
    • Asked in 30 of 32 Paper 3 sittings — nearly every paper.
    • About 8.8 marks a paper (12% of Paper 3; 71% of the topic's marks across its 2 bullets).
    • Last asked May/Jun 2026 · 9618/33 · Q6 (8 marks) — in the most recent series.
    • Asked in each of the last 11 series.
    • Easing: 9.8 → 8.8 marks a paper.
    • Usually “Complete” or “Write”: you must produce something — code, a diagram, a table — practise doing it, not reading it.
    • Biggest chunk of marks so far: 10 in Oct/Nov 2024 · 9618/31 · Q7.
    • It is examined almost entirely as AO2 (Apply & analyse, 79%) — you must apply it to the given data or scenario — work it out, trace it, explain it in context.
    Last 12 sittings↘ Easing
    Oct/Nov 24 · 31: 10 marksOct/Nov 24 · 32: 9 marksOct/Nov 24 · 33: 10 marksMay/Jun 25 · 31: 8 marksMay/Jun 25 · 32: 8 marksMay/Jun 25 · 33: 8 marksOct/Nov 25 · 31: 9 marksOct/Nov 25 · 32: 9 marksOct/Nov 25 · 33: 8 marksMay/Jun 26 · 31: 9 marksMay/Jun 26 · 32: 8 marksMay/Jun 26 · 33: 8 marks

    Assessment objectives

    • AO1 Knowledge & understanding
    • AO2 Apply & analyse
    • AO3 Design, program & evaluate
    • Complete92%
    • Write74%
    • Draw64%
    • Show40%
    Practise its 72 questionsBiggest: 10 marks · Oct/Nov 2024

5% of the topic's marks sit in question parts that belong to another topic (scenario questions cross sections) or that no bullet claims; they count for the topic, not for a bullet.

Marks a paper, year by year

151617181920212223242526

Grey years are the previous syllabus (2015–2021, 67 questions) — history, not counted in the rates.

By exam series

  • May/Jun18/18 · 13.6 mk
  • Oct/Nov14/14 · 12.9 mk
Practise 120 real questions Smart Notes Quiz Flashcards Every topic on the Statometer

What you need to know2syllabus §15.1, §15.2

  1. 15.1Processors, parallel processing and virtual machines — RISC vs CISC and interrupt handling; pipelining; SISD, SIMD, MISD, MIMD; massively parallel computers; virtual machines and their limits
  2. 15.2Boolean algebra and logic circuits — truth tables for circuits including half and full adders; SR and JK flip-flops as storage elements; Boolean algebra and De Morgan's laws; Karnaugh maps

Video lectures20ZAK's YouTube channel · play here

0 of 20 watched

  • A22024572 views

  • A22024204 views

  • A22024129 views

  • A22024435 views

  • A22024210 views

  • A22023595 views

Open in the video library ZAK's channel

Infographics6draw these the way the examiner expects · download as PNG

Half adder & full adderA half adder adds two bits. A full adder adds three (including a carry in) — two half adders plus an ORgate.Half adderABXORS = A ⊕ BANDC = A · BABSC0000011010101101Sum = XOR (1 if inputs differ)Carry = AND (1 only for 1 + 1)1 + 1 = 10₂ → S = 0, C = 1Full adderABCinHalf adder 1Half adder 2S1SC1C2ORCoutABCinSCout0000000110010100110110010101011100111111S = A ⊕ B ⊕ CinCout = A·B + Cin·(A ⊕ B)Chain n full adders,carry rippling along,to add n-bit numbers.Cin of the first = 0.Draw: two XORs feed the sum, the two carries are ORed. Label every wire — examiners mark the connections, not the boxes.cswithzak.com

Half adder & full adder

A2
SR & JK flip-flopsA flip-flop stores one bit. Two cross-coupled NAND gates make an SR flip-flop; the JK adds a clock andhas no invalid state.SR flip-flop (NAND)SRNANDNANDQQ̄SRQQ̄state11QQ̄hold (no change)0110SET1001RESET0011invalid — avoidInputs are active-low: a 0 on S sets Q to 1. Q and Q̄ must becomplements; S = R = 0 breaks that rule, and when both returnto 1 the output is unpredictable (race).JK flip-flopJClkKQQ̄JKJKQ (next)state00Qhold101SET010RESET11Q̄TOGGLE — no invalid stateChanges only on the clock edge (synchronous), so inputs can beset up in advance. Q feeds back to gate J and K — that is whatmakes J = K = 1 toggle and removes the SR invalid state.Flip-flops are built into registers, counters and static RAM. Learn the two truth tables and be able to explain each row.cswithzak.com

SR & JK flip-flops

A2
Karnaugh maps & Boolean algebraGroup 1s in blocks of 1, 2, 4, 8 (edges wrap); each group drops the variable that changes inside it.Bigger groups = simpler.Truth table → K-mapABCX00010010010101111000101011001111A \ BC000111100110110010column order is Gray code: 00 01 11 10 — only one bit changes each stepred (BC = 11, both rows) → B · Cblue (A = 0, BC = 11, 10) → Ā · Bamber (A = 0, BC = 00 & 10, wraps) → Ā · C̄X = B·C + Ā·B + Ā·C̄Boolean algebra lawsLawOR formAND formIdentityA + 0 = AA · 1 = ANullA + 1 = 1A · 0 = 0IdempotentA + A = AA · A = AComplementA + Ā = 1A · Ā = 0AbsorptionA + A·B = AA·(A + B) = ADistributiveA·(B + C) = A·B + A·CA + B·C = (A+B)·(A+C)De Morgan’s laws(A · B)‾ = Ā + B̄(A + B)‾ = Ā · B̄“Break the bar, change the sign.” Use them to convertNAND/NOR expressions and to simplify before drawinga circuit. Every NAND-only circuit relies on them.Sum-of-products: OR together one AND term per group. Check by substituting a truth-table row into your answer.cswithzak.com

Karnaugh maps & Boolean algebra

A2
RISC vs CISC & pipeliningRISC keeps instructions simple and uniform so several can be in the pipeline at once. CISC packs moreinto each one.RISCCISCInstructionsfew, simple, fixed length, one cycle eachmany, complex, variable length, multi-cycleAddressing modesfewmanyRegistersmany general-purposefewerHardwaresimpler processor, hardwired controlcomplex; microcodeCompiler / codemore instructions per programshorter programs, harder compilerPipeliningeasy — uniform instructionsharder5-stage pipeline — 4 instructions in flightcycle 1cycle 2cycle 3cycle 4cycle 5cycle 6cycle 7cycle 8Instr 1FDEMWInstr 2FDEMWInstr 3FDEMWInstr 4FDEMWF fetch · D decode · E execute · M memory access · W write back. No pipeline: 4 × 5 = 20 cycles. Pipelined: 8 cycles.Once full, one instruction completes every cycle. Hazard: a jump or interrupt makes the fetched instructions wrong → flush.Interrupt in a pipeline: finish the instructions already in flight, or flush them and save the state of every stage.cswithzak.com

RISC vs CISC & pipelining

A2
Parallel processing (Flynn) & virtual machinesFlynn's taxonomy classifies computers by how many instruction streams and data streams they handle atonce.SISDsingle instruction, single dataone processor works on one data item at a time — theclassic Von Neumann PCSIMDsingle instruction, multiple dataone instruction applied to many data items at once — GPU,array processor, vector mathsMISDmultiple instruction, single dataseveral processors run different instructions on the samedata — rare; fault-tolerant flight computersMIMDmultiple instruction, multiple datamany processors, each with its own instructions and data —multi-core CPUs, clusters, supercomputersMassively parallel computersThousands of processors, each with its own memory, linked bya fast network, cooperating by message passing. Software mustbe written to split the task — not every problem parallelises(dependencies, communication overhead, cost).Virtual machineGuest OS + appsHypervisor (VM software)Host hardware / host OSsoftware emulation ofa computer: runs anOS in a window, sharingthe real hardwarewith other guestsVM benefitsrun several OSs on one machine · test software safely · isolate untrusted programs · keep legacy systems alivecheaper than many physical servers · easy to copy, snapshot and restoreLimitationsslower — hardware is shared and emulated · needs a lot of RAM/CPU · some hardware not accessible · a host failure takes all guests downMnemonic: the first letter is the instruction stream (S/M), the second is the data stream. SIMD = same op on lots of data.cswithzak.com

Parallel processing & virtual machines

A2
From logic circuit to truth tableX = (A AND B) OR (NOT C). Work out the intermediate columns first — that is where the marks are.ABCANDNOTORXA AND BNOT CABCA AND BNOT CX000011001000010011011000100011101000110111111101Method1. Inputs: n inputs → 2ⁿ rows, count in binary 000 → 111.2. One column per gate output, left to right through the circuit.3. Final column X is the last gate’s output.4. Expression from circuit: work from inputs to output, bracketing each gate.Writing the expressionX = (A AND B) OR (NOT C)9618 Boolean algebra: X = A.B + C̄NAND/NOR/XOR circuits build the same way.Draw the correct gate shapes, inputs on the left, output on the right; lines that join must have a junction dot.Check: a circuit with 3 inputs must have 8 rows; a truth-table answer with fewer rows loses the mark.cswithzak.com

From logic circuit to truth table

O LevelASA2

Browse all infographics →

Key terms16use these exact words in the exam

RISCCISCpipeliningSISDSIMDMISDMIMDmassively parallelvirtual machinehypervisorhalf adderfull adderflip-flopBoolean algebraDe MorganKarnaugh map

Dotted terms are defined in the glossary.

Code help2referenced to the Cambridge pseudocode guide

Pipelining: what runs when

text
Cycle:   1    2    3    4    5    6
Instr 1: F    D    E
Instr 2:      F    D    E
Instr 3:           F    D    E
Instr 4:                F    D    E

4 instructions in 6 cycles instead of 12. A branch at Instr 2 would flush Instr 3–4.

Half adder and full adder as functions (§15.2)

pseudocode §8.2 functions Run in Playground
FUNCTION XOR(A : BOOLEAN, B : BOOLEAN) RETURNS BOOLEAN
   RETURN (A OR B) AND NOT (A AND B)
ENDFUNCTION
 
PROCEDURE FullAdder(A : BOOLEAN, B : BOOLEAN, Cin : BOOLEAN)
   DECLARE S1, C1, Sum, Cout : BOOLEAN
   S1 ← XOR(A, B)
   C1 ← A AND B
   Sum ← XOR(S1, Cin)
   Cout ← C1 OR (S1 AND Cin)
   OUTPUT A, " ", B, " ", Cin, " -> Sum ", Sum, " Carry ", Cout
ENDPROCEDURE
 
CALL FullAdder(TRUE, TRUE, FALSE)
CALL FullAdder(TRUE, TRUE, TRUE)

Boolean Algebra & K-map Lab35real Paper 3 questions — K-maps, De Morgan's laws, adders, flip-flops — solved and practised

  • Truth table, 6 ones → B.D + B̅.C̅.D̅

    June 2025 Q5: write the sum-of-products (2), complete the K-map (2), loop it (2), write the simplified sum-of-products (2).

    A2Truth table → K-map 9618 §15.2
    Open

  • Truth table → A.D + B̅.D → D.(A + B̅)

    Nov 2024 Q7, all five parts: sum-of-products (3), K-map (2), loops (2), simplified sum-of-products (2), simplest form by Boolean algebra (1).

    A2Truth table → K-map 9618 §15.2
    Open

  • Truth table → C̅.D + C.D̅ (no further simplification)

    Nov 2024 Q6: eight ones, two loops of four that cannot be factorised — the answer stays as a sum-of-products.

    A2Truth table → K-map 9618 §15.2
    Open

  • Truth table → A̅.B̅ + A̅.C → A̅.(B̅ + C)

    June 2023 Q9: two overlapping loops of four, then one factorising step for the simplest form.

    A2Truth table → K-map 9618 §15.2
    Open

  • Truth table → A.B + A.D → A.(B + D)

    Nov 2021 Q7: the examiners noted students simplified when the sum-of-products was asked for — write all six products first.

    A2Truth table → K-map 9618 §15.2
    Open

  • Truth table → B + C̅.D

    June 2026 Q7: a loop of eight (B) plus a loop of four wrapping the top and bottom rows.

    A2Truth table → K-map 9618 §15.2
    Open

  • Truth table → B̅.C + B.C̅.D̅

    June 2025 Q3: a loop of four in the bottom rows plus a loop of two — the two 1s in the top row are adjacent in the middle columns.

    A2Truth table → K-map 9618 §15.2
    Open

  • Three-variable truth table (A rows, BC columns)

    The 3-input map Cambridge draws with A down the side and BC along the top — a loop of four and a loop of two.

    A2ASTruth table → K-map 9618 §15.2
    Open

  • Six products → A.C + B.C → C.(A + B)

    June 2023 Q7: complete the K-map from the expression (2), loops (2), simplified sum-of-products (2), simplest form (1).

    A2Expression → K-map 9618 §15.2
    Open

  • Six products → B.C̅ + A.C̅ → C̅.(A + B)

    Nov 2022 Q7: the examiners saw one loop drawn round all six 1s, or six loops of two — both wrong. Two loops of four.

    A2Expression → K-map 9618 §15.2
    Open

  • Three-variable K-map → A + B̅

    June 2024 Q6(c): six products of A, B, C on the 2 × 4 map; two loops of four give A + B̅.

    A2Expression → K-map 9618 §15.2
    Open

  • Three-variable K-map → B + C̅ (wrapping loop)

    June 2024 Q6(c) variant 2: one loop of four wraps the outer columns (C̅) and one covers the middle two (B).

    A2Expression → K-map 9618 §15.2
    Open

  • Four products → A̅.B + B.C̅ + A.B̅.C

    Nov 2025 Q6(b): three loops — two of two and one lone 1 that stays a full three-literal product.

    A2Expression → K-map 9618 §15.2
    Open

  • The four corners are one loop → B̅.D̅

    Top-left, top-right, bottom-left and bottom-right cells are all adjacent on a K-map — one loop of four.

    A2Expression → K-map 9618 §15.2
    Open

  • K-map given → A̅.C̅.D + B.D + A.C

    Nov 2025 Q6(a): three loops for three marks — max 2 if any incorrect loop is drawn.

    A2Expression → K-map 9618 §15.2
    Open

  • K-map given → A.B + B.D + C.D

    June 2026 Q6(c): a loop of four (A.B), a loop of four (C.D) and a loop of four (B.D) overlapping both.

    A2Expression → K-map 9618 §15.2
    Open

  • (A + B + C̅)‾ + B̅.C → B̅.C

    June 2026 Q6(b): De Morgan's, double negation, then absorption — one mark for the answer, up to two for the laws.

    A2De Morgan's laws 9618 §15.2
    Open

  • (A.B.C.D)‾ + A̅.D̅ → A̅ + B̅ + C̅ + D̅

    June 2026 Q7(b): break the four-term bar, then the A̅.D̅ term is absorbed.

    A2De Morgan's laws 9618 §15.2
    Open

  • (A + B)‾.(A.B̅ + B.C)‾ → A̅.B̅

    June 2025 Q7(c), 4 marks: De Morgan's, then idempotent / distributive / absorption laws. The scheme also accepts (A + B)‾.

    A2De Morgan's laws 9618 §15.2
    Open

  • Bar over three barred products → A.(B + C) + B.D

    Nov 2022 Q8(c): a double-bar expression. The examiners' common error: splitting the bar but leaving AND as AND.

    A2De Morgan's laws 9618 §15.2
    Open

  • Apply De Morgan's to (A + B + C)‾

    Nov 2023 Q7(b): the 3-input NOR gate as an expression — one line, one mark.

    A2De Morgan's laws 9618 §15.2
    Open

  • (A + B̅ + C̅)‾ + (B + C̅)‾ → C.(A̅ + B̅)

    Nov 2025 Q6(b): De Morgan's twice, then the distributive and redundancy laws.

    A2De Morgan's laws 9618 §15.2
    Open

  • X̅.Y.Z + X̅.Y̅.Z + X → X + Z

    Nov 2023 Q7(c): distributive, complement, identity, then the redundancy law to finish.

    A2Boolean algebra 9618 §15.2
    Open

  • Four products → A.D̅

    Nov 2023 Q6(b): factor out A.D̅, then B.(C + C̅) + B̅.(C + C̅) collapses to 1 — the model working in the mark scheme.

    A2Boolean algebra 9618 §15.2
    Open

  • Absorption: A + A.B + A.B̅.C

    Two absorptions in a row — everything with an A in it collapses into A.

    A2Boolean algebra 9618 §15.2
    Open

  • Redundancy: A.B + A̅.C + B.C

    The consensus term B.C is covered by the other two — the K-map shows it as a loop you do not need.

    A2Boolean algebra 9618 §15.2
    Open

  • XOR as a sum-of-products

    A ⊕ B = A.B̅ + A̅.B — the half adder's sum output written in Boolean algebra.

    A2ASO LevelBoolean algebra 9618 §15.2
    Open

  • Circuit with working columns P, Q, R, S

    June 2024 Q6(a): P = A̅, Q = B.C, R = P NAND Q... build the working columns in gate order, then Z. One mark for the working, one per half of Z.

    A2ASO LevelCircuit → truth table 9618 §15.2
    Open

  • 3-input NAND circuit → truth table

    Nov 2023 Q6(a): a 3-input NAND feeding the output — the syllabus says gates “may have more than two inputs”.

    A2ASCircuit → truth table 9618 §15.2
    Open

  • 3-input NOR gate

    Nov 2023 Q7(a): X = (A + B + C)‾ — only one row of the truth table is 1.

    A2ASCircuit → truth table 9618 §15.2
    Open

  • Four working columns and an XOR

    Nov 2025 Q6(a) style: an XOR, a NAND and an OR feeding a final AND — eight rows, four working columns.

    A2ASO LevelCircuit → truth table 9618 §15.2
    Open

  • Half adder: name it, state Sum and Carry

    June 2022 Q6: two inputs A and B, outputs E (sum = A ⊕ B) and F (carry = A.B). 5 marks for the table, the name and the purposes.

    A2Half & full adders 9618 §15.2
    Open

  • Full adder: working columns, Sum and Carry as sums-of-products

    June 2021 Q7: complete P, Q, R, then Y (sum) and Z (carry); name the circuit; write Y and Z as sums-of-products — NOT simplified.

    A2Half & full adders 9618 §15.2
    Open

  • SR flip-flop: draw it, label S and R, find the invalid state

    Nov 2022 Q8: two NAND (or two NOR) gates, each output fed back to the other's input; purpose — to store one bit.

    A2Flip-flops 9618 §15.2
    Open

  • JK flip-flop: the toggle state SR cannot handle

    J = K = 1 toggles the output on the clock pulse — no invalid combination, which is why JK replaces SR.

    A2Flip-flops 9618 §15.2
    Open

Test yourself

Ready to check you know it?

Every round is a fresh random draw, weak cards come back until you get them right, and past-paper questions come with their mark schemes. Marks earn XP on your dashboard.

Quiz: Hardware & Virtual Machines (72)🃏 Flashcards: mix this topic (76)🧬 RISC vs CISC & pipelining (15)🧵 Parallel processing — Flynn's taxonomy (13)📦 Virtual machines (12)🧮 Boolean algebra & De Morgan's laws (16)🗺️ Karnaugh maps, adders & flip-flops (20)Past-paper questions (120)🗺️ Boolean Algebra & K-map Lab🔁 Adders & flip-flops⚡ Logic Gates Lab🚇 Pipelining & RISC/CISC🪤 Examiner's traps🎮 Play ArenaZ🎮 Play RoyaleZ🎮 Play GateZ🎮 Play SpireZ🎮 Play TycoonZ🎮 Play ImposterZ

NewCS Games · 16 to play

Revise this topic by playing

Quiz battles, a daily CS word, SQL whodunnits, logic-gate puzzles and arcade — every game drills the syllabus. Solo against AskZ bots, with friends, or with your whole class. Free, no sign-up.

Play now
ArenaZRoyaleZGateZSpireZTycoonZImposterZCodleZ+ all 16 →
Enroll nowOnline classes