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2210 · 0478Paper 1 · Computer Systems§3.1, §3.2, §3.3, §3.4

3. Hardware

The CPU and Von Neumann architecture, the fetch–decode–execute cycle, input/output devices, storage and virtual memory.

Statometer96BankerNext Paper 194%
Marks a paper22.5 · 30%Rank#2 of 10 · #1 on P1Trend · last 12Oct/Nov 24 · 13: 6 marksFeb/Mar 25 · 12: 32 marksMay/Jun 25 · 11: 20 marksMay/Jun 25 · 12: 21 marksMay/Jun 25 · 13: 16 marksOct/Nov 25 · 11: 31 marksOct/Nov 25 · 12: 40 marksOct/Nov 25 · 13: 30 marksFeb/Mar 26 · 12: 12 marksMay/Jun 26 · 11: 22 marksMay/Jun 26 · 12: 14 marksMay/Jun 26 · 13: 17 marks
9 in 10 chance in the next paper

Everything for this topic — study hub

O Level / IGCSE · 2210 · 0478 · Paper 1

Statometer — what 25 real papers say about this topic and each of its 5 syllabus bullets

Banker · #2 of 10 in O Level / IGCSE · recomputed with every new session

96BANKER
Banker#2 of 10 in O Level / IGCSE#1 on Paper 1 Easing

Set in nearly every paper and worth a big slice of it — revise first, expect it.

Next Paper 1
94%
9 in 10 chance it is set
Marks a paper
22.5 / 75
30% of Paper 1 · fair share 17%
Appeared in
25 / 25
Paper 1 sittings 20232026
Last set
May/Jun 2026
0478/13 · Q4 · 3 marks · 11-series streak
Marks in each of the last 12 Paper 1 sittingsOct/Nov 24May/Jun 26
Oct/Nov 24 · 13: 6 marksFeb/Mar 25 · 12: 32 marksMay/Jun 25 · 11: 20 marksMay/Jun 25 · 12: 21 marksMay/Jun 25 · 13: 16 marksOct/Nov 25 · 11: 31 marksOct/Nov 25 · 12: 40 marksOct/Nov 25 · 13: 30 marksFeb/Mar 26 · 12: 12 marksMay/Jun 26 · 11: 22 marksMay/Jun 26 · 12: 14 marksMay/Jun 26 · 13: 17 marks

What the papers say

  • Set in 25 of 25 Paper 1 sittings on the current syllabus — treat it as certain.
  • Worth about 22.5 marks a paper (30% of Paper 1, 1.8× its fair share).
  • Last set May/Jun 2026 · 0478/13 · Q4 for 3 marks — in the most recent series.
  • Set in each of the last 11 series without a miss.
  • Easing off: about 22.3 marks a paper earlier, 21.7 in the latest years — still examined, just smaller.
  • Lives on “Describe” and “Give” — 54% of its questions: full sentences with a reason, not one-word answers.
  • Most of its marks (85%) come in extended questions of 6+ marks — plan the answer before writing.
  • Its biggest question so far: 16 marks (Oct/Nov 2025 · 2210/12 · Q7).
  • Inside the topic, §3.2 Input and output devices carries the most marks (37%) and §3.1 CPU performance and embedded systems the least (4%).
  • §3.4 Network hardware has not been asked for 4 series — the bullet most likely to be “due”.
  • It is examined mostly as AO1 (Knowledge & understanding, 70%) — definitions and descriptions in syllabus words score.
  • The examiner has commented on 188 of its questions — read “What the examiner said” before you practise.
  • The single biggest share of Paper 1 among its 6 topics.

Command words

Share of questions using the word (a question can use several). What each wants →

Question shapes

  • 1–2 mk3
  • 3–4 mk49
  • 5–6 mk73
  • 7–9 mk82
  • 10+ mk68

Average 8 marks a question · 16% with a figure or table · 31% with code · biggest 16 marks

Assessment objectives — how it is examined

Every part of every current-syllabus question filed under Cambridge's AO1 / AO2 / AO3 (from its command word and what it asks you to do), so you know whether this topic pays for definitions, for applying, or for judging and building.

  • AO1 Knowledge & understanding
  • AO2 Apply to a context
  • AO3 Evaluate & judge

Paper 1 as a whole

Paper 1SyllabusMeasured
AO1 Knowledge & understanding60%64%
AO2 Apply to a context20%24%
AO3 Evaluate & judge20%12%

Syllabus = Cambridge's grid; measured = the bank's current-syllabus papers.

Inside the topic — every syllabus bullet, measured

Each part of each question is filed under the bullet it examines; the numbers are per Paper 1 sitting, exactly like the topic's. Open a bullet for its own Statometer.

  • 3.1Computer architecture#2 of 20 on Paper 1Banker · 9183% next paper7.1 marks21/25 sittings May/Jun 2026

    Asked in nearly every paper — the bullet to know cold.Syllabus: role of the CPU and the microprocessor; Von Neumann components (ALU, CU, PC, MAR, MDR, CIR, ACC, address/data/control buses); the fetch–decode–execute cycle

    Next Paper 1
    83%
    8 in 10
    Marks a paper
    7.1
    9% of the paper · 27% of the topic
    Asked in
    21 / 25
    Paper 1 sittings · 97 questions
    Last asked
    May/Jun 2026
    0478/13 · Q4 · 3 marks
    • Asked in 21 of 25 Paper 1 sittings — about 8 papers in 10.
    • About 7.1 marks a paper (9% of Paper 1; 27% of the topic's marks across its 5 bullets).
    • Last asked May/Jun 2026 · 0478/13 · Q4 (3 marks) — in the most recent series.
    • Usually “Identify” or “Explain”: short, precise answers in syllabus words.
    • Biggest chunk of marks so far: 10 in May/Jun 2025 · 0478/13 · Q3.
    • It is examined mostly as AO1 (Knowledge & understanding, 69%), the rest AO2 (30%) — definitions and descriptions in syllabus words score.
    Last 12 sittings Steady
    Oct/Nov 24 · 13: 6 marksFeb/Mar 25 · 12: 6.5 marksMay/Jun 25 · 11: 6 marksMay/Jun 25 · 12: 8 marksMay/Jun 25 · 13: 10 marksOct/Nov 25 · 11: 14 marksOct/Nov 25 · 12: 10 marksOct/Nov 25 · 13: 14 marksFeb/Mar 26 · 12: 0 marksMay/Jun 26 · 11: 5 marksMay/Jun 26 · 12: 7 marksMay/Jun 26 · 13: 3.5 marks

    Assessment objectives

    • AO1 Knowledge & understanding
    • AO2 Apply to a context
    • AO3 Evaluate & judge
    • Identify38%
    • Explain36%
    • Describe36%
    • Give32%
  • 3.1CPU performance and embedded systems#14 of 20 on Paper 1Regular · 5173% next paper2.4 marks18/25 sittings May/Jun 2026

    Set most sessions for a few marks; know the definition and one example.Syllabus: cores, cache and clock speed; the instruction set; purpose and characteristics of embedded systems and where they are used

    Next Paper 1
    73%
    7 in 10
    Marks a paper
    2.4
    3% of the paper · 4% of the topic
    Asked in
    18 / 25
    Paper 1 sittings · 25 questions
    Last asked
    May/Jun 2026
    0478/13 · Q3 · 4.5 marks
    • Asked in 18 of 25 Paper 1 sittings — about 7 papers in 10.
    • About 2.4 marks a paper (3% of Paper 1; 4% of the topic's marks across its 5 bullets).
    • Last asked May/Jun 2026 · 0478/13 · Q3 (4.5 marks) — in the most recent series.
    • Usually “Explain” or “Describe”: full sentences with a reason, not one-word answers.
    • Biggest chunk of marks so far: 5 in Oct/Nov 2025 · 2210/12 · Q4.
    • It is examined mostly as AO1 (Knowledge & understanding, 69%), the rest AO3 (31%) — definitions and descriptions in syllabus words score.
    Last 12 sittings Steady
    Oct/Nov 24 · 13: 0 marksFeb/Mar 25 · 12: 7 marksMay/Jun 25 · 11: 3 marksMay/Jun 25 · 12: 2 marksMay/Jun 25 · 13: 0 marksOct/Nov 25 · 11: 2 marksOct/Nov 25 · 12: 5 marksOct/Nov 25 · 13: 2.5 marksFeb/Mar 26 · 12: 0 marksMay/Jun 26 · 11: 2 marksMay/Jun 26 · 12: 2 marksMay/Jun 26 · 13: 4.5 marks

    Assessment objectives

    • AO1 Knowledge & understanding
    • AO2 Apply to a context
    • AO3 Evaluate & judge
    • Explain68%
    • Describe56%
    • State48%
    • Identify48%
  • 3.2Input and output devices#9 of 20 on Paper 1Core · 5966% next paper3.6 marks17/25 sittings May/Jun 2026

    A regular earner inside the topic — most papers touch it.Syllabus: input devices (scanners, camera, keyboard, microphone, mouse, touch screens), output devices (printers, projectors, screens, speakers, actuators) and the 14 sensors

    Next Paper 1
    66%
    7 in 10
    Marks a paper
    3.6
    5% of the paper · 37% of the topic
    Asked in
    17 / 25
    Paper 1 sittings · 135 questions
    Last asked
    May/Jun 2026
    0478/13 · Q3 · 3 marks
    • Asked in 17 of 25 Paper 1 sittings — about 7 papers in 10.
    • About 3.6 marks a paper (5% of Paper 1; 37% of the topic's marks across its 5 bullets).
    • Last asked May/Jun 2026 · 0478/13 · Q3 (3 marks) — in the most recent series.
    • Rising: 3.4 → 3.8 marks a paper.
    • Usually “Describe” or “Identify”: full sentences with a reason, not one-word answers.
    • Biggest chunk of marks so far: 10 in Oct/Nov 2025 · 2210/12 · Q7.
    • It is examined almost entirely as AO1 (Knowledge & understanding, 81%) — definitions and descriptions in syllabus words score.
    Last 12 sittings Rising
    Oct/Nov 24 · 13: 0 marksFeb/Mar 25 · 12: 4.5 marksMay/Jun 25 · 11: 0 marksMay/Jun 25 · 12: 0 marksMay/Jun 25 · 13: 0 marksOct/Nov 25 · 11: 4 marksOct/Nov 25 · 12: 13 marksOct/Nov 25 · 13: 0.5 marksFeb/Mar 26 · 12: 0 marksMay/Jun 26 · 11: 12.5 marksMay/Jun 26 · 12: 2 marksMay/Jun 26 · 13: 3 marks

    Assessment objectives

    • AO1 Knowledge & understanding
    • AO2 Apply to a context
    • AO3 Evaluate & judge
    • Describe42%
    • Identify34%
    • Explain30%
    • Give30%
  • 3.3Data storage#4 of 20 on Paper 1Banker · 8574% next paper6.3 marks20/25 sittings May/Jun 2026

    Asked in nearly every paper — the bullet to know cold.Syllabus: primary storage (RAM vs ROM), secondary storage (magnetic, optical and solid-state operation), virtual memory, and cloud storage vs local storage

    Next Paper 1
    74%
    7 in 10
    Marks a paper
    6.3
    8% of the paper · 27% of the topic
    Asked in
    20 / 25
    Paper 1 sittings · 98 questions
    Last asked
    May/Jun 2026
    2210/11 · Q4 · 2.5 marks · 4-series streak
    • Asked in 20 of 25 Paper 1 sittings — about 8 papers in 10.
    • About 6.3 marks a paper (8% of Paper 1; 27% of the topic's marks across its 5 bullets).
    • Last asked May/Jun 2026 · 2210/11 · Q4 (2.5 marks) — in the most recent series.
    • Asked in each of the last 4 series.
    • Easing: 6.9 → 5.5 marks a paper.
    • Usually “Explain” or “Give”: full sentences with a reason, not one-word answers.
    • Biggest chunk of marks so far: 12 in Feb/Mar 2026 · 0478/12 · Q5.
    • It is examined mostly as AO1 (Knowledge & understanding, 63%) — definitions and descriptions in syllabus words score.
    Last 12 sittings Easing
    Oct/Nov 24 · 13: 0 marksFeb/Mar 25 · 12: 0 marksMay/Jun 25 · 11: 11 marksMay/Jun 25 · 12: 11 marksMay/Jun 25 · 13: 6 marksOct/Nov 25 · 11: 5 marksOct/Nov 25 · 12: 8 marksOct/Nov 25 · 13: 10 marksFeb/Mar 26 · 12: 12 marksMay/Jun 26 · 11: 2.5 marksMay/Jun 26 · 12: 0 marksMay/Jun 26 · 13: 0 marks

    Assessment objectives

    • AO1 Knowledge & understanding
    • AO2 Apply to a context
    • AO3 Evaluate & judge
    • Explain43%
    • Give41%
    • Describe34%
    • Identify31%
  • 3.4Network hardware#19 of 20 on Paper 1Occasional · 1921% next paper1.1 marks6/25 sittings Feb/Mar 2025

    Rotated in occasionally — the bullet students skip and then meet.Syllabus: the network interface card, MAC addresses, IP addresses (IPv4 vs IPv6, static vs dynamic) and the role of a router

    Next Paper 1
    21%
    1 in 5 or less
    Marks a paper
    1.1
    2% of the paper · 5% of the topic
    Asked in
    6 / 25
    Paper 1 sittings · 17 questions
    Last asked
    Feb/Mar 2025
    0478/12 · Q5 · 7 marks · 4 series ago
    • Asked in 6 of 25 Paper 1 sittings — roughly one paper in 4.
    • About 1.1 marks a paper (2% of Paper 1; 5% of the topic's marks across its 5 bullets).
    • Not asked since Feb/Mar 2025 · 0478/12 · Q5 — 4 series ago. Bullets rotate inside a topic more than topics do: this one is due a turn.
    • Easing: 2.3 → 0.5 marks a paper.
    • Usually “Describe” or “Identify”: full sentences with a reason, not one-word answers.
    • Biggest chunk of marks so far: 7 in Feb/Mar 2025 · 0478/12 · Q5.
    • It is examined almost entirely as AO1 (Knowledge & understanding, 90%) — definitions and descriptions in syllabus words score.
    Last 12 sittings Easing
    Oct/Nov 24 · 13: 0 marksFeb/Mar 25 · 12: 7 marksMay/Jun 25 · 11: 0 marksMay/Jun 25 · 12: 0 marksMay/Jun 25 · 13: 0 marksOct/Nov 25 · 11: 0 marksOct/Nov 25 · 12: 0 marksOct/Nov 25 · 13: 0 marksFeb/Mar 26 · 12: 0 marksMay/Jun 26 · 11: 0 marksMay/Jun 26 · 12: 0 marksMay/Jun 26 · 13: 0 marks

    Assessment objectives

    • AO1 Knowledge & understanding
    • AO2 Apply to a context
    • AO3 Evaluate & judge
    • Describe59%
    • Identify53%
    • Tick35%
    • Give35%

15% of the topic's marks sit in question parts that belong to another topic (scenario questions cross sections) or that no bullet claims; they count for the topic, not for a bullet.

Marks a paper, year by year

1011121314151617181920212223242526

Grey years are the previous syllabus (20102022, 211 questions) — history, not counted in the rates.

By exam series

  • Feb/Mar4/4 · 19 mk
  • May/Jun12/12 · 20.1 mk
  • Oct/Nov9/9 · 27.8 mk

What you need to know5syllabus §3.1, §3.2, §3.3, §3.4

  1. 3.1Computer architecturerole of the CPU and the microprocessor; Von Neumann components (ALU, CU, PC, MAR, MDR, CIR, ACC, address/data/control buses); the fetch–decode–execute cycle
  2. 3.1CPU performance and embedded systemscores, cache and clock speed; the instruction set; purpose and characteristics of embedded systems and where they are used
  3. 3.2Input and output devicesinput devices (scanners, camera, keyboard, microphone, mouse, touch screens), output devices (printers, projectors, screens, speakers, actuators) and the 14 sensors
  4. 3.3Data storageprimary storage (RAM vs ROM), secondary storage (magnetic, optical and solid-state operation), virtual memory, and cloud storage vs local storage
  5. 3.4Network hardwarethe network interface card, MAC addresses, IP addresses (IPv4 vs IPv6, static vs dynamic) and the role of a router

Video lectures40ZAK's YouTube channel · play here

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Infographics3draw these the way the examiner expects · download as PNG

Von Neumann architectureOne memory holds both instructions and data; CPU and memory talk over three buses.CPUControl Unitdecodes, sends signalsALUarithmetic & logicRegistersPC · MAR · MDR · CIR · ACCCachefast memory for frequently used dataMain memoryRAM — instructions + dataaddress bus →data bus ⇄control bus ⇄Address bus is unidirectional (CPU → memory). Its width sets the maximum addressable memory (n lines → 2ⁿ addresses).cswithzak.com

Von Neumann architecture

O LevelAS
Fetch – Decode – Execute cycleRegister transfer notation for the fetch stage — learn it word for word.FETCHinstruction from memoryDECODEcontrol unit interprets opcodeEXECUTEALU / registers / memoryrepeat (check for interrupts at the end of each cycle)1. MAR ← [PC]2. PC ← [PC] + 13. MDR ← [[MAR]]4. CIR ← [MDR]address of next instruction → MARincrement ready for the next fetchcontents of that address → MDRcopy the instruction into CIRcswithzak.com

Fetch–Decode–Execute cycle

O LevelAS
Primary, secondary & virtual storagePrimary = accessed directly by the CPU. Secondary = permanent, not directly accessed. Off-line =removable. Cloud = remote.PRIMARYRAM — volatile, read/write; holds therunning programs and data; more RAM= fewer swaps to virtual memory.ROM — non-volatile, read-only; holds thefirmware / bootstrap loader (BIOS)that starts the computer.SECONDARYMagnetic (HDD): spinning platters,r/w heads; cheap per GB; moving parts.Optical (CD/DVD/Blu-ray): laser readspits & lands on a spiral track.Solid state (SSD, flash): NAND transistors,no moving parts — fast, quiet, robust.OFF-LINE / CLOUDRemovable: USB flash, external HDD,optical discs — backups and transfer.Cloud: files stored on remote servers,accessed over the internet.+ anywhere access, automatic backup– needs connection, privacy, cost.Virtual memoryRAMpages of running programsHDD / SSDswap / page filepage out (not needed now)page in (needed again)Lets programs biggerthan RAM run; moreprograms at once.Slower than RAM;disk thrashing whenpages swap constantly.Why secondary storage? RAM is volatile — unsaved work is lost at power-off. Why RAM? It is far faster than any secondary storage.Sizes: bit → nibble → byte → KiB → MiB → GiB → TiB (×1024). Embedded systems keep their program in ROM/flash.cswithzak.com

Primary, secondary & virtual storage

O Level

Browse all infographics →

Key terms17use these exact words in the exam

CPUALUCUMARMDRPCaccumulatorbusfetch–decode–executecacheembedded systemRAMROMvirtual memoryrouterMAC addressIPv4/IPv6

Dotted terms are defined in the glossary.

Code help2referenced to the Cambridge pseudocode guide

Fetch–decode–execute in register transfer notation

text
MAR ← [PC]          ; address of next instruction → MAR
PC  ← [PC] + 1      ; ready for the next fetch
MDR ← [[MAR]]       ; contents of that address → MDR
CIR ← [MDR]         ; instruction → CIR
; decode in the CU, then execute (ALU / registers / memory)

💡 Not on the 2210 exam as RTN, but memorising it makes the FDE description questions easy.

Simulating a simple register add

pseudocode Run in Playground
DECLARE ACC, MDR : INTEGER
ACC 5 // value already in the accumulator
MDR 7 // value fetched from memory
ACC ACC + MDR
OUTPUT "ACC = ", ACC

Playground examples1runnable program for this topic

  • Fetch–decode–execute simulator

    A tiny CPU: PC and ACC registers, instructions in memory, one loop that fetches, decodes with CASE and executes.

    ASPseudocodeTheory in code 9618 §4.1, §4.3
    Run

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