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2210 · 0478Paper 1 · Computer Systems§3.1, §3.2, §3.3, §3.4

3. Hardware

The CPU and Von Neumann architecture, the fetch–decode–execute cycle, input/output devices, storage and virtual memory.

In the 2029–31 syllabus the CPU and storage become Topic 2; network hardware moves to 3.2–3.3 (now with IPv4/IPv6 and static/dynamic IP), cloud storage models are added and legacy media are removed. What changes in 2029 → · Study the new topics: 2. Logic circuits and hardware, 3. Data transmission and networking, 6. Automated systems and robotics

Statometer96BankerNext Paper 194%
Marks a paper23.3 · 31%Rank#2 of 10 · #1 on P1Trend · last 12→Oct/Nov 24 · 13: 6 · Feb/Mar 25 · 12: 32 · May/Jun 25 · 11: 20 · May/Jun 25 · 12: 8 · May/Jun 25 · 13: 16 · Oct/Nov 25 · 11: 37 · Oct/Nov 25 · 12: 40 · Oct/Nov 25 · 13: 30 · Feb/Mar 26 · 12: 12 · May/Jun 26 · 11: 22 · May/Jun 26 · 12: 24 · May/Jun 26 · 13: 29 marks
9 in 10 chance in the next paper

Everything for this topic — study hub

O Level / IGCSE · 2210 · 0478 · Paper 1

This topic is rows 8–12 of the study route.Open it on your study route

Statometer — what 25 real papers say about this topic and each of its 5 syllabus bullets

Banker · #2 of 10 in O Level / IGCSE · recomputed with every new session

96BANKER
Banker#2 of 10 in O Level / IGCSE#1 on Paper 1→ Steady

Set in nearly every paper and worth a big slice of it — revise first, expect it.

Next Paper 1
94%
9 in 10 chance it is set
Marks a paper
23.3 / 75
31% of Paper 1 · fair share 17%
Appeared in
25 / 25
Paper 1 sittings 2023–2026
Last set
May/Jun 2026
0478/13 · Q4 · 3 marks · 11-series streak
Marks in each of the last 12 Paper 1 sittingsOct/Nov 24 → May/Jun 26
Oct/Nov 24 · 13: 6 marksFeb/Mar 25 · 12: 32 marksMay/Jun 25 · 11: 20 marksMay/Jun 25 · 12: 8 marksMay/Jun 25 · 13: 16 marksOct/Nov 25 · 11: 37 marksOct/Nov 25 · 12: 40 marksOct/Nov 25 · 13: 30 marksFeb/Mar 26 · 12: 12 marksMay/Jun 26 · 11: 22 marksMay/Jun 26 · 12: 24 marksMay/Jun 26 · 13: 29 marks

What the papers say

  • Set in 25 of 25 Paper 1 sittings on the current syllabus — treat it as certain.
  • Worth about 23.3 marks a paper (31% of Paper 1, 1.9× its fair share).
  • Last set May/Jun 2026 · 0478/13 · Q4 for 3 marks — in the most recent series.
  • Set in each of the last 11 series without a miss.
  • Steady at around 24 marks a paper year on year.
  • Lives on “Give” and “Describe” — 53% of its questions: short, precise answers in syllabus words.
  • Most of its marks (86%) come in extended questions of 6+ marks — plan the answer before writing.
  • Its biggest question so far: 16 marks (Oct/Nov 2025 · 2210/12 · Q7).
  • Inside the topic, §3.2 Input and output devices carries the most marks (34%) and §3.1 CPU performance and embedded systems the least (4%).
  • It is examined mostly as AO1 (Knowledge & understanding, 71%) — definitions and descriptions in syllabus words score.
  • The examiner has commented on 175 of its questions — read “What the examiner said” before you practise.
  • The single biggest share of Paper 1 among its 6 topics.

Command words

Share of questions using the word (a question can use several). What each wants →

Question shapes

  • 1–2 mk3
  • 3–4 mk37
  • 5–6 mk64
  • 7–9 mk71
  • 10+ mk69

Average 8 marks a question · 17% with a figure or table · 33% with code · biggest 16 marks

Assessment objectives — how it is examined

Every part of every current-syllabus question filed under Cambridge's AO1 / AO2 / AO3 (from its command word and what it asks you to do), so you know whether this topic pays for definitions, for applying, or for judging and building.

  • AO1 Knowledge & understanding
  • AO2 Apply to a context
  • AO3 Evaluate & judge

Paper 1 as a whole

Paper 1SyllabusMeasured
AO1 Knowledge & understanding60%64%
AO2 Apply to a context20%24%
AO3 Evaluate & judge20%12%

Syllabus = Cambridge's grid; measured = the bank's current-syllabus papers.

Inside the topic — every syllabus bullet, measured

Each part of each question is filed under the bullet it examines; the numbers are per Paper 1 sitting, exactly like the topic's. Open a bullet for its own Statometer.

  • 3.1Computer architecture#3 of 20 on Paper 1Banker · 8883% next paper6.3 marks21/25 sittings→ May/Jun 2026

    Asked in nearly every paper — the bullet to know cold.Syllabus: role of the CPU and the microprocessor; Von Neumann components (ALU, CU, PC, MAR, MDR, CIR, ACC, address/data/control buses); the fetch–decode–execute cycle

    Next Paper 1
    83%
    8 in 10
    Marks a paper
    6.3
    8% of the paper · 27% of the topic
    Asked in
    21 / 25
    Paper 1 sittings · 80 questions
    Last asked
    May/Jun 2026
    0478/13 · Q4 · 3 marks
    • Asked in 21 of 25 Paper 1 sittings — about 8 papers in 10.
    • About 6.3 marks a paper (8% of Paper 1; 27% of the topic's marks across its 5 bullets).
    • Last asked May/Jun 2026 · 0478/13 · Q4 (3 marks) — in the most recent series.
    • Usually “Identify” or “Give”: short, precise answers in syllabus words.
    • Biggest chunk of marks so far: 10 in May/Jun 2025 · 0478/13 · Q3.
    • It is examined mostly as AO1 (Knowledge & understanding, 70%), the rest AO2 (30%) — definitions and descriptions in syllabus words score.
    Last 12 sittings→ Steady
    Oct/Nov 24 · 13: 6 marksFeb/Mar 25 · 12: 6.5 marksMay/Jun 25 · 11: 6 marksMay/Jun 25 · 12: 6 marksMay/Jun 25 · 13: 10 marksOct/Nov 25 · 11: 6 marksOct/Nov 25 · 12: 10 marksOct/Nov 25 · 13: 14 marksFeb/Mar 26 · 12: 0 marksMay/Jun 26 · 11: 5 marksMay/Jun 26 · 12: 7 marksMay/Jun 26 · 13: 3.5 marks

    Assessment objectives

    • AO1 Knowledge & understanding
    • AO2 Apply to a context
    • AO3 Evaluate & judge
    • Identify40%
    • Give33%
    • Describe31%
    • Explain30%
  • 3.1CPU performance and embedded systems#15 of 20 on Paper 1Regular · 4868% next paper2.3 marks17/25 sittings→ May/Jun 2026

    Set most sessions for a few marks; know the definition and one example.Syllabus: cores, cache and clock speed; the instruction set; purpose and characteristics of embedded systems and where they are used

    Next Paper 1
    68%
    7 in 10
    Marks a paper
    2.3
    3% of the paper · 4% of the topic
    Asked in
    17 / 25
    Paper 1 sittings · 23 questions
    Last asked
    May/Jun 2026
    0478/13 · Q3 · 4.5 marks
    • Asked in 17 of 25 Paper 1 sittings — about 7 papers in 10.
    • About 2.3 marks a paper (3% of Paper 1; 4% of the topic's marks across its 5 bullets).
    • Last asked May/Jun 2026 · 0478/13 · Q3 (4.5 marks) — in the most recent series.
    • Usually “Explain” or “Describe”: full sentences with a reason, not one-word answers.
    • Biggest chunk of marks so far: 5 in Oct/Nov 2025 · 2210/12 · Q4.
    • It is examined mostly as AO1 (Knowledge & understanding, 72%), the rest AO3 (28%) — definitions and descriptions in syllabus words score.
    Last 12 sittings→ Steady
    Oct/Nov 24 · 13: 0 marksFeb/Mar 25 · 12: 7 marksMay/Jun 25 · 11: 3 marksMay/Jun 25 · 12: 2 marksMay/Jun 25 · 13: 0 marksOct/Nov 25 · 11: 0 marksOct/Nov 25 · 12: 5 marksOct/Nov 25 · 13: 2.5 marksFeb/Mar 26 · 12: 0 marksMay/Jun 26 · 11: 2 marksMay/Jun 26 · 12: 2 marksMay/Jun 26 · 13: 4.5 marks

    Assessment objectives

    • AO1 Knowledge & understanding
    • AO2 Apply to a context
    • AO3 Evaluate & judge
    • Explain70%
    • Describe61%
    • State44%
    • Identify44%
  • 3.2Input and output devices#11 of 20 on Paper 1Core · 5864% next paper3.6 marks16/25 sittings↗ May/Jun 2026

    A regular earner inside the topic — most papers touch it.Syllabus: input devices (scanners, camera, keyboard, microphone, mouse, touch screens), output devices (printers, projectors, screens, speakers, actuators) and the 14 sensors

    Next Paper 1
    64%
    6 in 10
    Marks a paper
    3.6
    5% of the paper · 34% of the topic
    Asked in
    16 / 25
    Paper 1 sittings · 112 questions
    Last asked
    May/Jun 2026
    0478/13 · Q3 · 3 marks
    • Asked in 16 of 25 Paper 1 sittings — about 6 papers in 10.
    • About 3.6 marks a paper (5% of Paper 1; 34% of the topic's marks across its 5 bullets).
    • Last asked May/Jun 2026 · 0478/13 · Q3 (3 marks) — in the most recent series.
    • Rising: 2.7 → 4.2 marks a paper.
    • Usually “Identify” or “Describe”: short, precise answers in syllabus words.
    • Biggest chunk of marks so far: 10 in Oct/Nov 2025 · 2210/12 · Q7.
    • It is examined almost entirely as AO1 (Knowledge & understanding, 81%) — definitions and descriptions in syllabus words score.
    Last 12 sittings↗ Rising
    Oct/Nov 24 · 13: 0 marksFeb/Mar 25 · 12: 4.5 marksMay/Jun 25 · 11: 0 marksMay/Jun 25 · 12: 0 marksMay/Jun 25 · 13: 0 marksOct/Nov 25 · 11: 9 marksOct/Nov 25 · 12: 13 marksOct/Nov 25 · 13: 0.5 marksFeb/Mar 26 · 12: 0 marksMay/Jun 26 · 11: 12.5 marksMay/Jun 26 · 12: 2 marksMay/Jun 26 · 13: 3 marks

    Assessment objectives

    • AO1 Knowledge & understanding
    • AO2 Apply to a context
    • AO3 Evaluate & judge
    • Identify38%
    • Describe36%
    • Give36%
    • Explain31%
  • 3.3Data storage#4 of 20 on Paper 1Banker · 8883% next paper6.2 marks22/25 sittings↘ May/Jun 2026

    Asked in nearly every paper — the bullet to know cold.Syllabus: primary storage (RAM vs ROM), secondary storage (magnetic, optical and solid-state operation), virtual memory, and cloud storage vs local storage

    Next Paper 1
    83%
    8 in 10
    Marks a paper
    6.2
    8% of the paper · 30% of the topic
    Asked in
    22 / 25
    Paper 1 sittings · 98 questions
    Last asked
    May/Jun 2026
    0478/13 · Q1 · 5 marks · 4-series streak
    • Asked in 22 of 25 Paper 1 sittings — nearly every paper.
    • About 6.2 marks a paper (8% of Paper 1; 30% of the topic's marks across its 5 bullets).
    • Last asked May/Jun 2026 · 0478/13 · Q1 (5 marks) — in the most recent series.
    • Asked in each of the last 4 series.
    • Easing: 7.1 → 5.7 marks a paper.
    • Usually “Explain” or “Give”: full sentences with a reason, not one-word answers.
    • Biggest chunk of marks so far: 12 in Feb/Mar 2026 · 0478/12 · Q5.
    • It is examined mostly as AO1 (Knowledge & understanding, 67%), the rest AO3 (22%) — definitions and descriptions in syllabus words score.
    Last 12 sittings↘ Easing
    Oct/Nov 24 · 13: 0 marksFeb/Mar 25 · 12: 0 marksMay/Jun 25 · 11: 11 marksMay/Jun 25 · 12: 0 marksMay/Jun 25 · 13: 6 marksOct/Nov 25 · 11: 5 marksOct/Nov 25 · 12: 8 marksOct/Nov 25 · 13: 10 marksFeb/Mar 26 · 12: 12 marksMay/Jun 26 · 11: 2.5 marksMay/Jun 26 · 12: 3 marksMay/Jun 26 · 13: 5 marks

    Assessment objectives

    • AO1 Knowledge & understanding
    • AO2 Apply to a context
    • AO3 Evaluate & judge
    • Explain42%
    • Give41%
    • Describe36%
    • State31%
  • 3.4Network hardware#19 of 20 on Paper 1Occasional · 2226% next paper1.4 marks7/25 sittings↘ Oct/Nov 2025

    Rotated in occasionally — the bullet students skip and then meet.Syllabus: the network interface card, MAC addresses, IP addresses (IPv4 vs IPv6, static vs dynamic) and the role of a router

    Next Paper 1
    26%
    1 in 4
    Marks a paper
    1.4
    2% of the paper · 5% of the topic
    Asked in
    7 / 25
    Paper 1 sittings · 18 questions
    Last asked
    Oct/Nov 2025
    0478/11 · Q2 · 5 marks · 2 series ago
    • Asked in 7 of 25 Paper 1 sittings — roughly one paper in 4.
    • About 1.4 marks a paper (2% of Paper 1; 5% of the topic's marks across its 5 bullets).
    • Last asked Oct/Nov 2025 · 0478/11 · Q2 (5 marks), 2 seriess ago.
    • Easing: 2.3 → 0.9 marks a paper.
    • Usually “Describe” or “Identify”: full sentences with a reason, not one-word answers.
    • Biggest chunk of marks so far: 7 in Feb/Mar 2025 · 0478/12 · Q5.
    • It is examined almost entirely as AO1 (Knowledge & understanding, 91%) — definitions and descriptions in syllabus words score.
    Last 12 sittings↘ Easing
    Oct/Nov 24 · 13: 0 marksFeb/Mar 25 · 12: 7 marksMay/Jun 25 · 11: 0 marksMay/Jun 25 · 12: 0 marksMay/Jun 25 · 13: 0 marksOct/Nov 25 · 11: 5 marksOct/Nov 25 · 12: 0 marksOct/Nov 25 · 13: 0 marksFeb/Mar 26 · 12: 0 marksMay/Jun 26 · 11: 0 marksMay/Jun 26 · 12: 0 marksMay/Jun 26 · 13: 0 marks

    Assessment objectives

    • AO1 Knowledge & understanding
    • AO2 Apply to a context
    • AO3 Evaluate & judge
    • Describe56%
    • Identify50%
    • Give44%
    • Tick39%

15% of the topic's marks sit in question parts that belong to another topic (scenario questions cross sections) or that no bullet claims; they count for the topic, not for a bullet.

Marks a paper, year by year

1011121314151617181920212223242526

Grey years are the previous syllabus (2010–2022, 178 questions) — history, not counted in the rates.

By exam series

  • Feb/Mar4/4 · 18.8 mk
  • May/Jun12/12 · 20.7 mk
  • Oct/Nov9/9 · 28.4 mk

What you need to know5syllabus §3.1, §3.2, §3.3, §3.4

  1. 3.1Computer architecture — role of the CPU and the microprocessor; Von Neumann components (ALU, CU, PC, MAR, MDR, CIR, ACC, address/data/control buses); the fetch–decode–execute cycle
  2. 3.1CPU performance and embedded systems — cores, cache and clock speed; the instruction set; purpose and characteristics of embedded systems and where they are used
  3. 3.2Input and output devices — input devices (scanners, camera, keyboard, microphone, mouse, touch screens), output devices (printers, projectors, screens, speakers, actuators) and the 14 sensors
  4. 3.3Data storage — primary storage (RAM vs ROM), secondary storage (magnetic, optical and solid-state operation), virtual memory, and cloud storage vs local storage
  5. 3.4Network hardware — the network interface card, MAC addresses, IP addresses (IPv4 vs IPv6, static vs dynamic) and the role of a router

Video lectures43ZAK's YouTube channel · play here

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Infographics3draw these the way the examiner expects · download as PNG

Von Neumann architectureOne memory holds both instructions and data; CPU and memory talk over three buses.CPUControl Unitdecodes, sends signalsALUarithmetic & logicRegistersPC · MAR · MDR · CIR · ACCCachefast memory for frequently used dataMain memoryRAM — instructions + dataaddress bus →data bus ⇄control bus ⇄Address bus is unidirectional (CPU → memory). Its width sets the maximum addressable memory (n lines → 2ⁿ addresses).cswithzak.com

Von Neumann architecture

O LevelAS
Fetch – Decode – Execute cycleRegister transfer notation for the fetch stage — learn it word for word.FETCHinstruction from memoryDECODEcontrol unit interprets opcodeEXECUTEALU / registers / memoryrepeat (check for interrupts at the end of each cycle)1. MAR ← [PC]2. PC ← [PC] + 13. MDR ← [[MAR]]4. CIR ← [MDR]address of next instruction → MARincrement ready for the next fetchcontents of that address → MDRcopy the instruction into CIRcswithzak.com

Fetch–Decode–Execute cycle

O LevelAS
Primary, secondary & virtual storagePrimary = accessed directly by the CPU. Secondary = permanent, not directly accessed. Off-line =removable. Cloud = remote.PRIMARYRAM — volatile, read/write; holds therunning programs and data; more RAM= fewer swaps to virtual memory.ROM — non-volatile, read-only; holds thefirmware / bootstrap loader (BIOS)that starts the computer.SECONDARYMagnetic (HDD): spinning platters,r/w heads; cheap per GB; moving parts.Optical (CD/DVD/Blu-ray): laser readspits & lands on a spiral track.Solid state (SSD, flash): NAND transistors,no moving parts — fast, quiet, robust.OFF-LINE / CLOUDRemovable: USB flash, external HDD,optical discs — backups and transfer.Cloud: files stored on remote servers,accessed over the internet.+ anywhere access, automatic backup– needs connection, privacy, cost.Virtual memoryRAMpages of running programsHDD / SSDswap / page filepage out (not needed now)page in (needed again)Lets programs biggerthan RAM run; moreprograms at once.Slower than RAM;disk thrashing whenpages swap constantly.Why secondary storage? RAM is volatile — unsaved work is lost at power-off. Why RAM? It is far faster than any secondary storage.Sizes: bit → nibble → byte → KiB → MiB → GiB → TiB (×1024). Embedded systems keep their program in ROM/flash.cswithzak.com

Primary, secondary & virtual storage

O Level

Browse all infographics →

Key terms17use these exact words in the exam

Code help2referenced to the Cambridge pseudocode guide

Fetch–decode–execute in register transfer notation

text
MAR ← [PC]          ; address of next instruction → MAR
PC  ← [PC] + 1      ; ready for the next fetch
MDR ← [[MAR]]       ; contents of that address → MDR
CIR ← [MDR]         ; instruction → CIR
; decode in the CU, then execute (ALU / registers / memory)

💡 Not on the 2210 exam as RTN, but memorising it makes the FDE description questions easy.

Simulating a simple register add

pseudocode Run in Playground
DECLARE ACC, MDR : INTEGER
ACC ← 5 // value already in the accumulator
MDR ← 7 // value fetched from memory
ACC ← ACC + MDR
OUTPUT "ACC = ", ACC

Playground examples1runnable program for this topic

  • Fetch–decode–execute simulator

    A tiny CPU: PC and ACC registers, instructions in memory, one loop that fetches, decodes with CASE and executes.

    ASPseudocodeTheory in code 9618 §4.1, §4.3
    Run

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